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Certified ASIC Verification Course (VS-CAVC)
 
Course Overview:
Verification takes 70 % of the time in total ASIC flow while creating a new chip. System Verilog has emerged as the most versatile language to handle Verification.
Today a leading electronic system contains more than a billion gates and millions of lines of code. This increase in design complexity has created manifold challenges in design verification. This not only is fuelled need for advancements in verification technologies, but also created huge need for the professionals in functional verification to achieve time to market. System Verilog is also the stepping stone for UVM.
This training is a thorough dive into advanced functional verification technologies such as SystemVerilog
This course covers:
  • Verification plan development
  • Verification environment creation
  • Test case development
  • Functional Coverage
  • Regression development
Duration:50 Days (30 days theory and practical classes + 20 days Project).
Timings: Monday - Friday (10 AM - 5 PM)
Prerequisites:
  • B.E / B.Tech / M.E / M.Tech with background in Electronics, should have minimum aggregate of 60% throughout academic career.
  • Strong knowledge in Digital design Concepts.
  • Good Knowledge in RTL design and Verification using Verilog HDL/VHDL.
  • Good logical & analytical ability.
 
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