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Certified UVM Course (VS-CUVMC)
 
Course Overview:
Verification takes 70 % of the time in total ASIC flow while creating a new chip. Verification of complex ASIC/SOC is made easy with Universal Verification Methodologies (UVM). It is an extension of SystemVerilog.
Today a leading electronic system contains more than a billion gates and millions of lines of code. This increase in design complexity has created manifold challenges in design verification. This not only is fuelled need for advancements in verification technologies, but also created huge need for the professionals in functional verification to achieve time to market.
This training is a thorough dive into advanced functional verification technologies such as UVM.
Duration:30 Days (20 days theory and practical classes + 10 days Project).
Timings: Monday - Friday (10 AM - 5 PM)
Prerequisites:
  • B.E / B.Tech / M.E / M.Tech with background in Electronics, should have minimum aggregate of 60% throughout academic career.
  • Good knowledge of digital design, RTL Design using Verilog HDL.
  • Strong knowledge of RTL Verification using SystemVerilog.
  • Good logical & analytical ability.
 
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