Login
 
+91 96320 66600  |
 
Contact Us
Consulting
Home
Topic: FPGA Based RTL Design 
Date: 19-08-2017/b>
Timings: 10 AM to 5 PM.
Venue: Verilogic Solutions,
#9, 1st Main road, Dollors colony, RMV 2nd stage, Bangalore -94.
Contents:
  • Verilog HDL Basics
    • Data Types
    • Operators
  • Levels of abstraction
    • Gate Level Modeling
    • Dataflow modeling
    • Behavioral modeling
        • Initial
        • Always
        • Blocking and non blocking assignments
  • Conditional Statements
    • If-else statements
    • Case statements
  • System Tasks
  • Basic Test-bench writing
  • RTL simulation
  • RTL Synthesis
  • FPGA prototyping
After attending the Workshop the student will get:
  • Good knowledge of RTL design and RTL Synthesis.
  • Hands on experience of FPGA prototyping.
  • Exposure to advanced industry SW/HW tools.
  • Participation certificate.
  • Internship opportunity.
Last Date for Registration: 1st Oct 2016.
Free Workshop   Form :
 
Copyright ©2015-2017 verilogic.in, All rights reserved. 
Powered & Designed By Crazy Curve