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IP Verification (VS-IPV) 
Course Overview :
An Intellectual Property (IP) in VLSI is a reusable unit of logic or functionality or a cell like USB, Ethernet, DDR, AXI, UART, etc. Today, a leading electronic system contains more than a billion gates and millions of lines of code. This increase in design complexity has created manifold challenges in IP verification. This not only is fuelled need for advancements in verification technologies, but also created huge need for the professionals in functional verification to achieve time to market.
This training is a thorough dive into advanced functional verification technologies such as SystemVerilog and UVM. It provides a step-by-step guide to build scalable, reusable and flexible verification environment to verify complex IP designs.
Duration : 6 Weekends (12 Days)
Timings : Saturday & Sunday (10 AM - 6 PM)
Prerequisites :
  • B.E / B.Tech / M.E / M.Tech with background in Electronics, should have minimum aggregate of 60% throughout academic career
  • Basic knowledge in Verilog
  • Good knowledge on Digital design
  • Good logical & analytical ability
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