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Low Power Design Verfication (VS-LPDV) 
Course Overview:
Low power design and verification are increasingly necessary in today's world, as electronic devices become increasingly portable, power and cooling become increasingly expensive, and consumer demand for more features with less power drive product development. The Unified Power Format (UPF), enables low power design and verification in multi vendor flows, from early RTL verification of the power management architecture through physical design and implementation.
This course will give an overview of SOC and UPF based low power design verification and implementation, as well as examples of UPF application from both the IP developer's and the system integrators perspective.
This training is a thorough dive into advanced functional verification technologies such as SystemVerilog and UVM.
Duration:6 Weekends (12 Days)
Timings: Saturday & Sunday (10 AM - 6 PM)
  • B.E / B.Tech / M.E / M.Tech with background in Electronics, should have minimum aggregate of 60% throughout academic career
  • Basic knowledge on C Programming
  • Good knowledge on any Processor architectures
  • Good logical & analytical ability
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