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VIP Development 
With ever increasing size of ASIC and FPGA, complexity of verification is increasing exponentially. Every small change in design is resulting in long verification cycle. As a result, 50-70% of chip development resources are now getting consumed by verification efforts. With processor now part of SoC, complexity of verification has increased further.
Our team has extensive experience in taking up full responsibility or being part of larger customer team, delivering module to full-chip verification for complex chips. We have worked with simple verification environment created by using simple Verilog or VHDL to full coverage driven random environment in SystemVerilog using UVM. Our team has developed reusable Verification components from scratch as well as used industry standard VIPs as part of environment to reduce time and improve quality of verification.
We have extensive experience in :
  • VIP development for interfaces such as Ethernet, USB, AHB/AXI, I2C, etc
  • VIP development using HVL such as SystemVerilog.
  • VIP development using latest methodologies such as UVM, OVM, VMM, etc.
These VIPs are very easy to integrate and use in any verification environment. They can be used for directed testing or coverage driven testing to achieve maximum code and functional coverage. There VIPs reduce overall verification time and effort drastically.
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